1. Field of the Invention
The present invention relates to semiconductor fabrication, and in particular relates to compound semiconductor devices using gallium arsenide (GaAs) substrates and methods for fabricating the same, wherein elements comprising conductive materials therein can be provided with improved electrical stress performance.
2. Description of the Related Art
Gallium arsenide (GaAs) is one of the known compound semiconductor materials which has high electron mobility (typically about six times greater than that of silicon material), high saturated drifting speeds, and semi-insulating properties; therefore, being suitable for being applied in fabrication processes such as high-speed device fabrication. In addition, Gallium arsenide material also shows properties such as high output efficiency, low power consumption, low noise, etc. which are good for fabrication of high frequency communication devices capable of replacing conventional low frequency silicon communication devices to thereby satisfy needs of modern communication and network applications.
FIG. 1 shows a conventional compound semiconductor device 150 fabricated over a gallium arsenide (GaAs) substrate 100. Herein, for the purpose of simplicity, only a portion of the compound semiconductor device 150 is illustrated.
As shown in FIG. 1, similar with the conventional silicon semiconductor devices fabricated over a silicon substrate, the compound semiconductor device 150 comprises an integrated circuit made of a plurality of different elements. Elements which form the integrated circuit in the compound semiconductor device 150 comprise, for example, active elements such as transistors or diodes, and passive elements such as resistors and capacitors, and other elements such as conductive pads. These elements all comprise conductive materials therein.
For the purpose of simplicity, only two adjacent elements A and B are illustrated in FIG. 1, and these two elements A and B can be same or different elements which are selected from the elements mentioned above.
Although the GaAs substrate 100 is a semi-insulating substrate, the elements A and B of the compound semiconductor device 150, however, typically comprise device layers made of conductive materials, such as P-doped or N-doped channel layers and ohmic contact layers. Due to physical connections of these device layers with the GaAs substrate 100, conductive dopants or metal elements in the conductive materials may be diffused into the GaAs substrate 100 during fabrication or operation of the compound semiconductor device 150; thereby causing undesired inter-diffusion effects and producing undesired electrical conductivity for portions of the GaAs substrate 100 adjacent to the elements A and B.
Therefore, once large currents such as ESD currents are conducted to the element A and/or the element B, the large currents may migrate along a current path E1 (illustrated in dashed lines) extending along a top surface of the GaAs substrate 100 between the elements A and B and cause electromigration of the adjacent elements A and B. This may cause electrical breakdown of the elements A and B and also cause malfunction of the compound semiconductor device 150.
Therefore, to prevent undesired electrical breakdown of the elements, a pitch P1 must be set between the elements A and B to prevent occurrence of the undesired electromigration. The size of the pitch P1 can be determined according to fabrication processes of the elements A and B, and is typically about 20-300 microns.
Requirement of the pitch P1, however, may restrict the amount of elements that may be provided over the GaAs substrate 100, and is not advantageous for size reduction of the compound semiconductor device 150.
FIGS. 2-5 are schematic diagrams showing conventional elements which may be implemented as the elements A and B formed over the GaAs substrate 100.
In FIG. 2, a conventional transistor 10 is illustrated, comprising a channel layer 102, an ohmic contact layer 106, passivation layers 110 and 116, a gate electrode 108 and contact electrodes 114. Herein, for the purpose for simplicity, the channel layer 102 is illustrated as a single layer, but it is typically formed of a plurality of stacked sub-layers comprising P-type and/or N-type doped GaAs materials and/or undoped GaAs materials. In addition, a source region, a drain region and a channel region (all not shown) can be respectively formed in a portion in the channel layer 102. The ohmic contact layer 106 can be respectively disposed over the source region and the drain region, and the ohmic contact layer 106 may comprise stacked sub-layers made of AuGe, Ni, and Au. The gate electrode 108 is disposed over a portion of the channel region. The passivation layer 110 conformably covers portions of the GaAs substrate 110, the channel layer 102, the ohmic contact layers 106, the gate electrode 108. The contact electrodes 114 are respectively formed over portions of the passivation layer 110, the ohmic contact layer 106, and the gate electrode 108. In addition, another passivation layer 116 partially covers the passivation layer 110 and the contact electrode 114, and an opening 118 is formed in a portion thereof to expose a portion of each of the contact electrodes 108. In FIG. 3, a cross section taken along line 3-3 in FIG. 2 is illustrated, showing configurations in the source region or the drain region.
FIGS. 4 and 5 show a conventional capacitor 20 and a conventional conductive pad 30, respectively. As shown in FIGS. 4 and 5, the capacitor 20 and the conductive pad 30 are formed from the device layers similar with those formed in the transistor 10 as shown in FIGS. 2-3, and the capacitor 20 and the conductive pad 30 can be simultaneously formed during fabrication of the transistor 10. In the figures, the same references represent the same components. The contact electrode 114 formed in the capacitor 20 can function as a top electrode and the passivation layer 110 may function as a capacitance layer, and the gate electrode 108 and the ohmic contact layer 110 may function as a bottom electrode. The conductive pad 30 shown in FIG. 5 may comprise an ohmic contact layer 106, and can thus electrically contact the conductive electrode 114 of the GaAs substrate 100 through the ohmic contact layer 106.
Thus, to improve integration of elements in the compound semiconductor device 150 and reduce chip size thereof, a novel layout design of the compound semiconductor device is desired.